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Computers, personal digital assistants, cellular telephones and other electronic systems and devices typically include processors and memory. The memory is used to store instructions (typically in the form of computer programs) to be executed and/or data to be operated on by the processors to achieve the functionality of the device. Jn some applications, the systems and devices may require that the instructions and/or data be retained in some form of a permanent/non-volatile storage medium so that the information is not lost when the device is turned off or power is removed. Exemplary applications include computer BIOS storage and diskless handheld computing devices such as personal digital assistants.
One way to provide such non-volatile storage capability is to include a mass-storage device such as a hard disk drive. Hard disk drives are mechanical devices which store data on rotating magnetic platters. However, such devices may be difficult to fit in small systems and may have significant reliability, cost and manufacturing constraints. An alternative to such devices are integratedcircuit based non-volatile memories. One type of non-volatile memory that can be used is Erasable Programmable Read Only Memory (xe2x80x9cEPROMxe2x80x9d). While conventional EPROM""s provide reliable non-volatile storage, they may not be able to be reprogrammed in the field in a practical manner. For example, EPROM""s typically require exposure to ultraviolet light to erase them which may require that the EPROM memory chips be removed from the device. Once erased and reprogrammed, they are placed back in the device. In many applications, removing the memory to reprogram the device is not practical. In addition, besides not being easily reprogrammed, EPROM""s may not have satisfactory data storage densities.
To avoid the complexity of EPROM""s and to provide a device that can be reprogrammed in the field, many electronic designs use Electrically Erasable Programmable Read Only Memory (xe2x80x9cEEPROMxe2x80x9d), Static Random Access Memory (xe2x80x9cSRAMxe2x80x9d) or flash memory, which can be reprogrammed electrically and without special hardware. SRAM is not technically a form of non-volatile memory but can be used in some applications requiring non-volatile capability.
EEPROM has the disadvantages of being expensive and having a very limited life cycle, i.e. an EEPROM can only be erased and rewritten a limited number of times before the device becomes non-functional. SRAM offers high operating speeds but only maintains its contents as long as power is supplied, therefore requiring a battery or other power source. This necessitates additional hardware to maintain power to the SRAM to preserve the stored contents which increases manufacturing cost and complexity. Further, the additional hardware may put undesirable constraints on the physical size of the design. In addition, EEPROM""s and SRAM""s may not have as high a data storage density as compared to other forms of storage. Therefore, where cost, size or density is a factor, flash memories are preferred because they may be simpler to reprogram in the field then EPROM""s, less expensive than EEPROM""s, easier to implement than battery-backed SRAM""s and available in higher data storage densities.
Flash memory (or flash RAM) is a form of non-volatile storage which uses a memory cell design with a floating gate. High voltages are applied to the memory cell inputs to program/store charge on the floating gate or to erase/remove charge from the floating gate. Programming occurs by hot electron transfer to place charge on the floating gate while erasure makes use of Fowler-Nordheim tunneling in which electrons pierce through a thin dielectric material, reducing the amount of electronic charge on the floating gate. Erasing a cell sets the logical value of the cell to xe2x80x9c1xe2x80x9d while programming the cell sets the logical value to xe2x80x9c0xe2x80x9d. Aside from programming or erasing operations, a flash memory operates similarly to a randomly accessible read only memory (ROM). Conventionally, a flash memory chip, including the flash memory storage cells and support logic/circuitry, is made by fabricating layers of semiconductor material and interconnect layers of polysilicon and first and second metal layers onto a substrate. It will be appreciated that there are numerous integrated circuit fabrication techniques, involving more or fewer layers, which are applicable herein.
Prior flash memories could only be erased by erasing the entire memory chip also known as bulk erasure. Byte by byte erasure was not possible. To somewhat alleviate this problem, modern flash memory is typically divided logically into blocks called xe2x80x9csectorsxe2x80x9d where each sector contains a portion of the total bytes of data storage available. For example, a typical flash memory may have 32 megabits of total storage and be logically broken down into 64 sectors, each sector containing 64 Kilobytes of data (one byte being equal to eight bits). This arrangement allows for the option of erasure of one sector at a time in addition to bulk erasure of the entire memory. While typical flash memories are still incapable of byte by byte erasure, data in the flash memory may still be programmed byte by byte (or sometimes word by word, where a word equals two or four bytes) depending on the implementation. It will be appreciated that the granularity by which a flash memory device can be programmed or erased may vary and that granularities down to bit level programming/erasure are contemplated.
In order to program and/or erase a flash memory, typically a complex process must be followed. For example, before erasing a particular sector, that sector must be programmed (known as xe2x80x9cpre-programmingxe2x80x9d). These steps of erasing and programming involve complex application of high voltages to the memory cells for specified periods of time and in particular sequences. Many flash memories provide embedded state machines which perform the complex programming and erasing operations automatically. These processes of programming and erasing a flash memory may take a long time to complete. A typical erase sequence can take anywhere from 0.7 seconds up to 15 seconds per sector. To erase an entire chip can take up to 49 seconds depending on the number of sectors. While programming is much faster, on the order of 7 to 300 microseconds per byte, it is still slow compared to other memory devices. Programming an entire chip can still take up to 120 seconds (including the time to verify the data) depending on the capacity of the chip. Typically, standard Dynamic Random Access Memory (xe2x80x9cDRAMxe2x80x9d) offers write access times on the order of nano-seconds, a difference between flash memory of many orders of magnitude.
Another problem with existing flash memory devices has been the low density of storage offered as compared with traditional dynamic random access memory (xe2x80x9cDRAMxe2x80x9d). With the ever increasing need for storage space in modem electronic devices combined with the need to reduce the number of discrete components, there has been a corresponding pressure to increase the amount of storage available on a single flash memory device. This increase in storage density must not come at the expense of reliability.
One way to increase the storage capacity of a flash memory device is to use a core cell with a dual-level floating gate structure. Such a structure allows one core cell to represent more than one bit of information without increasing the size/area of the device. However, such dual-level core cells are difficult to design and implement because they require complex programming, erase and read logic. This is because the multiple voltage levels that can be stored in the cell now represent more than one logical value and the programming, erase and read logic must now be able to discriminate among these voltage levels. This raises concerns with the ability of the flash memory device to reliably store and retrieve data.
The present invention is defined by the following claims, and nothing in this section should be taken as a limitation on those claims. By way of introduction, the preferred embodiments described below relate to a sense amplifier output equalization circuit for a high density flash memory device comprising an array of single level flash memory cells capable of operating with a variable voltage. The sense amplifier output equalization circuit comprise an equalization pulse generator coupled with the sense amplifier output and operative to generate an equalization pulse to equalize the sense amplifier output. The equalization pulse is characterized by a duration. The circuit further comprises a delay circuit coupled with the equalization pulse generator and operative to control the duration of the equalization pulse and a variable adjustment circuit coupled with the delay circuit and operative to adjust the duration as a function of the variable voltage.
The preferred embodiments also relate to a method of equalizing outputs of sense amplifier of a high density flash memory device capable of operating with a variable voltage. The method comprises: asserting an equalization signal to the sense amplifiers; deasserting the equalization signal after elapse of a variable period of time; and adjusting the variable period of time as a function of the variable voltage.